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d a t a sh eet preliminary speci?cation file under integrated circuits, ic17 1998 mar 20 integrated circuits tda8005a low-power (3 v/5 v) smart card coupler
1998 mar 20 2 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a features smart card supply (5 and 3 v 5%, 20 ma maximum with controlled rise and fall times) smart card clock generation (up to 8 mhz), with two times synchronous frequency doubling clock stop high, clock stop low or 1.25 mhz (from internal oscillator) for cards power-down mode specific uart on i/o for automatic direct/inverse convention settings and error management at character level automatic activation and deactivation sequences through an independent sequencer supports the protocol t = 0 in accordance with iso 7816 gsm11.11 requirements (global system for mobile communication); approved for final gsm11.11 test approval (fta) several analog options are available for different applications: doubler or tripler dc-to-dc converter, card presence, active high or low, threshold voltage supervisor, etc. overloads and take-off protections current limitations in the event of short-circuit special circuitry for killing spikes during power-on or off supply supervisor step-up converter (supply voltage from 2.5 to 6 v) power-down and sleep mode for low power consumption enhanced electrostatic discharge (esd) protections on card side (6 kv minimum) control and communication through a standard rs232 full-duplex interface optional additional i/o ports for: C keyboard C leds C display C etc. p80cl51 microcontroller core with 4-kbyte rom and 256-byte ram. applications portable smart card readers for protocol t = 0 gsm mobile phones. general description the tda8005a is a low-cost card interface for portable smart card readers. controlled through a standard serial interface, it takes care of all iso 7816 and gsm11.11 requirements for both 5 and 3 v cards. it gives the card and the set a very high level of security, due to its special hardware against esd, short-circuiting, power failure, etc. its integrated step-up converter allows operation within a supply voltage range of 2.5 to 6 v. the very low power consumption in power-down and sleep modes saves battery power. development tools, application report and support (hardware and software) are available. ordering information type number package name description version TDA8005AG lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 tda8005ah qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
1998 mar 20 3 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a quick reference data note 1. see table 3 for mask options. symbol parameter conditions min. typ. max. unit v dd supply voltage doubler and tripler option 2.5 - 6.0 v i dd(pd) supply current in power-down mode v dd = 5 v; card inactive - 100 -m a i dd(sm) supply current in sleep mode card powered but clock stopped; no load doubler option - 500 -m a tripler option - 700 -m a i dd(om) supply current in operating mode unloaded; f xtal = 13 mhz; f m c = 6.5 mhz; f card = 3.25 mhz - 5.5 - ma v cc card supply voltage 5 v card no load 4.85 5.05 5.25 v static load 4.75 5.0 5.25 v dynamic load on 200 nf capacitor 4.5 - 5.4 v 3 v card no load 2.9 3.03 3.15 v static load 2.79 3 3.21 v dynamic load on 200 nf capacitor 2.75 - 3.25 v i cc card supply current operating -- 20 ma limitation -- note 1 ma sr slew rate on v cc (rise and fall) maximum load capacitor 250 nf (including typical 200 nf decoupling) 0.04 0.1 0.16 v/ m s t de deactivation sequence duration -- 225 m s t act activation sequence duration -- 150 m s f xtal crystal frequency 2 - 16 mhz t amb operating ambient temperature - 25 - +85 c
1998 mar 20 4 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a block diagram fig.1 block diagram. pin numbers in parenthesis represent the tda8005ah. (1) for details see chapter pinning and table 3. handbook, full pagewidth voltage sense 2.3 to 2.7 v internal oscillator 2.5 mhz TDA8005AG (tda8005ah) internal reference supply alarm delay reset aux1 aux2 int1 xtal1 xtal2 dgnd agnd p00 (1) to p37 rxd txd optional ports peripheral interface controller cl51 iso 7816 uart clock circuitry output port extension step-up converter 4 kbytes rom 256-byte ram security v cc generator rst buffer i/o buffer clock buffer sequencer s1 s2 47 nf 100 nf 100 nf s3 s4 47 nf v ddd v dda 2.5 to 6 v 63 (43) 10 (7) 44 46 (31) 22 (17) 28 (18) 29 (19) 32 (22) 33 (23) 30 (20) 36 (26) 35 (25) 37 (27) 2 (1) 53 k0 k1 k2 k3 k4 k5 52 51 50 49 47 (32) 57 (37) 55 (35) 56 (36) 58 (38) 59 (39) 4 up s5 v 60 (40) 47 nf lis v cc 100 nf rst i/o clk pres en1 en2 en3 en4 start rst off 64 (44) 61 (41) 3 (2) 62 (42) alarm v ddd skill data clk en s0 s1 r/w micro- controller clock i/o int ref v ddd osc ref osc mgl330
1998 mar 20 5 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a pinning symbol pin description lqfp64 qfp44 n.c. 1 - not connected agnd 2 1 analog ground s3 3 2 contact 3 for the step-up converter k5 4 - output port from port extension p03 5 3 general purpose i/o port (connected to port p03) p02 6 4 general purpose i/o port (connected to port p02) p01 7 5 general purpose i/o port (connected to port p01) n.c. 8 - not connected p00 9 6 general purpose i/o port (connected to port p00) v ddd 10 7 digital supply voltage n.c. 11 - not connected test1 12 8 test pin 1 (connected to port p10; must be left open-circuit in the application) p11 13 9 general purpose i/o port or interrupt (connected to port p11) p12 14 10 general purpose i/o port or interrupt (connected to port p12) p13 15 11 general purpose i/o port or interrupt (connected to port p13) p14 16 12 general purpose i/o port or interrupt (connected to port p14) n.c. 17 - not connected p15 18 13 general purpose i/o port or interrupt (connected to port p15) p16 19 14 general purpose i/o port or interrupt (connected to port p16) test2 20 15 test pin 2 (connected to psen; must be left open-circuit in the application) p17 21 16 general purpose i/o port or interrupt (connected to port p17) reset 22 17 input for resetting the microcontroller (active high) n.c. 23 - not connected n.c. 24 - not connected n.c. 25 - not connected n.c. 26 - not connected n.c. 27 - not connected rxd 28 18 serial interface receive line txd 29 19 serial interface transmit line int1 30 20 general purpose i/o port or interrupt (connected to port p33) t0 31 21 general purpose i/o port (connected to port p34) aux1 32 22 push-pull auxiliary output ( 5 ma; connected to timer t1 e.g. port p35) aux2 33 23 push-pull auxiliary output ( 5 ma; connected to timer; port p36) p37 34 24 general purpose i/o port (connected to port p37) xtal2 35 25 crystal connection xtal1 36 26 crystal connection or external clock input dgnd 37 27 digital ground n.c. 38 - not connected
1998 mar 20 6 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a n.c. 39 - not connected p20 40 28 general purpose i/o port (connected to port p20) p21 41 - general purpose i/o port (connected to port p21) p22 42 29 general purpose i/o port (connected to port p22) p23 43 30 general purpose i/o port (connected to port p23) alarm 44 - open-drain output for power-on reset (active high or low by mask option) n.c. 45 - not connected delay 46 31 external capacitor connection for delayed reset signal pres 47 32 card presence contact input (active high or low by mask option) test3 48 33 test pin 3 (must be left open-circuit in the application) k4 49 - output port from port extension k3 50 - output port from port extension k2 51 - output port from port extension k1 52 - output port from port extension k0 53 - output port from port extension test4 54 34 test pin 4 (must be left open-circuit in the application) i/o 55 35 data line to/from the card (iso c7 contact) rst 56 36 card reset output (iso c2 contact) clk 57 37 clock output to the card (iso c3 contact) v cc 58 38 card supply output voltage (iso c1 contact) lis 59 39 supply for low-impedance on cards contacts s5 60 40 contact 5 for the step-up converter s2 61 41 contact 2 for the step-up converter s4 62 42 contact 4 for the step-up converter v dda 63 43 analog supply voltage s1 64 44 contact 1 for the step-up converter symbol pin description lqfp64 qfp44
1998 mar 20 7 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.2 pin configuration (lqfp64). handbook, full pagewidth TDA8005AG mgl331 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 n.c. p14 agnd s3 k5 p03 p02 p01 n.c. p00 v n.c. test1 p11 p12 p13 ddd n.c. aux1 p15 p16 test2 p17 reset n.c. n.c. n.c. n.c. rxd txd int1 t0 n.c. test3 pres delay n.c. alarm p23 p22 p21 p20 n.c. n.c. dgnd xtal1 xtal2 p37 aux2 v s1 s4 s2 s5. lis v clk rst i/o test4 k0 k1 k2 k3 k4 dda cc
1998 mar 20 8 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.3 pin configuration (qfp44). handbook, full pagewidth tda8005ah mgl332 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 agnd s3 p03 p02 p01 p00 ddd test1 p11 p12 p13 v p14 p15 p16 test2 p17 reset rxd txd int1 t0 aux1 test3 pres delay p23 p22 p20 dgnd xtal1 xtal2 p37 aux2 s1 v s4 s2 s5 lis v clk rst i/o test4 dda cc
1998 mar 20 9 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a functional description microcontroller the microcontroller is a p80cl51 with 256 bytes of ram instead of 128. the baud rate of the uart has been multiplied by four in modes 1, 2 and 3. this means that the division factor of 32 in the formula is replaced by 8 in both reception and transmission mode and that in the reception modes only four samples per bit are taken with decision on the majority of samples 2, 3 and 4; the delay counter has been reduced from 1536 to 24 as well. remark: this has an impact when getting out of power-down mode. it is recommended to switch to internal clock before entering power-down mode. all the other functions remain unchanged. refer to the p80cl51 data sheet for any further information. internal ports int0 (p32), p10, p04 to p07 and p24 to p27 are used for controlling the smart card interface. mode 0 is unchanged. the baud rate for modes 1 and 3 is: the baud rate for mode 2 is: for mode 3 timing see table 1. table 1 mode 3 timing baud rate f clk = 6.5 mhz; v dd =5v f clk = 3.25 mhz; v dd =5or3v smod th1 smod th1 135416 1 255 -- 67708 0 255 1 255 45139 1 253 -- 33854 0 254 0 255 27083 1 251 -- 22569 0 253 1 253 16927 -- 0 254 13542 -- 1 251 11285 0 250 0 253 2 smod 8 ---------------- - f clk 12 256 th1 C () ---------------------------------------------- - 2 smod 16 ---------------- - f clk supply the circuit operates within a supply voltage range of 2.5 to 6 v. the supply pins are v ddd , v dda , dgnd and agnd. pins v dda and agnd supply the analog drivers to the card and have to be externally decoupled because of the large current spikes that the card and the step-up converter can create. an integrated spike killer ensures the contacts to the card remain inactive during power-up or power-down. an internal voltage reference is generated which is used within the step-up converter, the voltage supervisor and the v cc generator. the voltage supervisor generates an internal alarm pulse, whose length is defined by an external capacitor tied to the delay pin, when v ddd is too low to ensure proper operation (1 ms per 1 nf typical). this pulse is used as a reset pulse by the controller, in parallel with an external reset input, which can be tied to the system controller. it is also used in order to either block any spurious card contacts during controllers reset, or to force an automatic deactivation of the contacts in the event of supply dropout; see sections activation sequence and deactivation sequence. in the 64 pin version, this reset pulse is output to the open drain alarm pin, which may be selected active high or active low by mask option and may be used as a reset pulse for other devices within the application.
1998 mar 20 10 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.4 supply supervisor. handbook, full pagewidth mgl333 v th(vdd) + v hys(vthvdd) v th(vdd) v th(delay) v delay alarm v dd low impedance supply (pin lis) for some applications, it is mandatory that the contacts to the card (v cc , rst, clk and i/o) are low impedance while the card is inactive and also when the coupler is not powered. an auxiliary supply voltage on pin lis ensures this condition where i lis 5 m a for v lis = 5 v. this low impedance situation is disabled when v cc starts rising during activation, and re-enabled when the step-up converter is stopped during deactivation. if this feature is not required, the lis pin must be tied to v ddd . step-up converter except for the v cc generator and the other cards contacts buffers, the whole circuit is powered by v ddd and v dda . if the supply voltage is 3 or 5 v, then a higher voltage is needed for the iso contacts supply. when a card session is requested by the controller, the sequencer first starts the step-up converter, which is a switched capacitors type, clocked by an internal oscillator at a frequency of approximately 2.5 mhz. the output voltage v step-up is regulated at approximately 6.5 v and then fed to the v cc generator. v cc and dgnd are used as a reference for all other cards contacts. the step-up converter may be chosen as a doubler or a tripler by mask option, depending on the voltage and the current needed on the card. iso 7816 security the correct sequence during activation and deactivation of the card is ensured through a specific sequencer, clocked by a division ratio of the internal oscillator. activation (start signal p05; see table 3) is only possible if the card is present (pres high or low according to mask option), and if the supply voltage is correct (alarm signal inactive); clk and rst are controlled by rstin (internal signal; port p04), allowing the correct count of clk pulses during answer-to-reset from the card. the presence of the card is signalled to the controller by the off signal (port p10; see table 3). during a session, the sequencer performs an automatic emergency deactivation in the event of card take-off, supply voltage drop, or hardware problems. the off signal falls thereby warning the controller.
1998 mar 20 11 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a clock circuitry the clock to the microcontroller and the clock to the card are derived from the main clock signal (xtal from 2 to 16 mhz, or an external clock signal). directly after reset and during power reduction modes the microcontroller clock frequency f clk equals 1 8 f int ; f int is always present because it is derived from the internal oscillator and gives the lowest power consumption. when required (for card session, serial communication or anything else) the microcontroller may choose to clock itself with 1 2 f xtal , 1 4 f xtal or 1 2 f int . all frequency changes are synchronous, thereby ensuring no hang-up due to short spikes etc. cards clock: the microcontroller may select to send the card a card clock frequency of 1 2 f xtal , 1 4 f xtal , 1 8 f xtal or 1 2 f int ( ? 1.25 mhz), or to stop the clock high or low. all transitions are synchronous, ensuring correct pulse length during start or change in accordance with iso 7816. after power on, clk is set at stop low and f clk is set at 1 8 f int . power-down and sleep modes the tda8005a offers a large flexibility for defining power reduction modes by software. some configurations are described below. in the power-down mode, the microcontroller is in power-down and the supply and the internal oscillator are active. the card is not active; this is the smallest power consumption mode. any change on p1 ports or on pres will wake-up the circuit (for example, a key pressed on the keyboard, the card inserted or taken off). in the sleep mode, the card is powered but configured in the idle or sleep mode. the step-up converter will only be active when it is necessary to reactivate v step-up . when the microcontroller is in power-down mode any change on p1 ports or on pres will wake up the circuit. in both power reduction modes the sequencer is active, allowing automatic emergency deactivation in the event of card take-off, hardware problems, or supply dropout. the tda8005a is set into power-down or sleep mode by software. there are several ways to return to normal mode: insertion or extraction of the card, detection of a change on p1 (which can be a key pressed) or a command from the system microcontroller. for example, if the system monitors the clock signal on xtal1, it may stop this clock after setting the device into power-down mode and then wake it up when sending the clock signal again. in this situation, the internal clock should have been used before the f clk . peripheral interface this block allows synchronous serial communication with the three peripherals (iso 7816 uart, clock circuitry and output port extension); see figs 1 and 5. fig.5 peripheral interface diagram. handbook, full pagewidth mgl334 cc0 cc1 cc2 cc3 cc4 cc5 cc6 cc7 clock configuration reset uc0 uc1 uc2 uc3 uc4 uc5 uc6 uc7 uart configuration ut0 ut1 ut2 ut3 ut4 ut5 ut6 ut7 uart transmit ur0 ur1 ur2 ur3 ur4 ur5 ur6 ur7 uart receive peripheral control us0 us1 us2 us3 us4 us5 us6 us7 uart status register pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 ports extension p07 enable p06 strobe p24 data p27 reg0 p26 reg1 p25 r/w p32 int
1998 mar 20 12 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a table 2 explanation of fig.5; note 1 note 1. all registers are active high. bit name description reg0 = 0, reg1 = 0 and r/ w = 0; clock con?guration register (con?guration after reset is cards clock stop low, f clk = 1 8 f int ) cc0 cards clock = 1 2 f xtal cc1 cards clock = 1 4 f xtal cc2 cards clock = 1 8 f xtal cc3 cards clock = 1 2 f int cc4 cards clock = stop high cc5 f clk = 1 2 f xtal cc6 f clk = 1 4 f xtal cc7 f clk = 1 2 f int reg0 = 1, reg1 = 0 and r/ w = 0; uart con?guration register (after reset all bits are cleared) uc0 iso uart reset uc1 start session uc2 lct (last character to transmit) uc3 transmit/receive uc4 3 v/5 v uc5 to uc7 not used reg0 = 0, reg1 = 1 and r/ w = 0; uart transmit register ut0 to ut7 lsb to msb of the character to be transmitted to the card reg0 = 1, reg1 = 1 and r/ w = 0; ports extension (after reset all bits are cleared) pe0 to pe5 pe0 to pe5 is the inverse of the value to be written on k0 to k5 pe6 and pe7 not used reg0 = 0, reg1 = 0 and r/ w = 1; uart receive register ur0 to ur7 lsb to msb of the character received from the card reg0 = 1, reg1 = 0 and r/ w = 1; uart status register (after reset all bits are cleared) us0 uart transmit buffer empty us1 uart receive buffer full us2 ?rst start bit detected us3 parity error detected during reception of a character (the uart has asked the card to repeat the character) us4 parity error detected during transmission of a character; the controller must write the previous character in the uart transmit register, or abort the session us5 to us7 not used
1998 mar 20 13 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a u se of peripheral interface write operation 1. select the correct register with r/ w, reg0 and reg1 2. write the word in the peripheral shift register (psr) with data and strobe; data is shifted on the rising edge of strobe; 8 shifts are necessary 3. give a negative pulse on enable; the data is parallel loaded in the register on the falling edge of enable. read operation 1. select the correct register with r/ w, reg0 and reg1 2. give a first negative pulse on enable; the word is parallel loaded in the peripheral shift register on the rising edge of enable 3. give a second negative pulse on enable for configuring the psr in shift right mode 4. read the word from psr with data and strobe; data is shifted on the rising edge of strobe; 7 shifts are necessary. e xample of peripheral interface ;**************************************** ;*change of clock configuration register* ;**************************************** ; ;**the new configuration is supposed** ;**to be in the accumulator** clr reg0 clr reg1 clr r/ w mov r2,#8 loop rrc a mov data c clr strobe set strobe djnz r2,loop clr enable set enable set data ret ;**************************************** ;*read character arrived in uart receive* ;*****************register*************** ;**************************************** ; ;**the character will be in the** ;**accumulator** clr reg0 clr reg1 set r/ w clr enable set enable clr enable set enable mov r2,#8 loop mov c,data rrc a clr strobe set strobe djnz r2,loop set data ret iso uart the iso uart handles all the specific requirements defined in iso t = 0 protocol type. it is clocked with the cards clock, which gives the f clk /31 sampling rate for start bit detection (the start bit is detected at the first low level on i/o) and the f clk /372 frequency for elementary time unit (etu) timing (in the reception mode the bit is sampled at 1 2 etu). it also allows the cards clock frequency changes without interfering with the baud rate. this hardware uart allows operating of the microcontroller at low frequency, thus lowering em radiations and power consumption. it also frees the microcontroller of fastidious conversions and real time jobs thereby allowing the control of higher level tasks. the following occurs in the reception mode (see fig.6): detection of the inverse or direct convention at the beginning of answer to reset (atr) automatic convention setting, so the microcontroller only receives characters in direct convention parity checking and automatic request for character repetition in case of error (reception is possible at 12 etu).
1998 mar 20 14 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a the following occurs in the transmission mode (see fig.7): transmission according to the convention detected during atr, consequently the microcontroller only has to send characters in direct convention; transmission of the next character may start at 12 etu in the event of no error or 13 etu in case of error parity calculation and detection of repetition request from the card in the event of error the bit lct (last character to transmit) allows fast reconfiguration for receiving the answer 12 etu after the start bit of the last transmitted character. the iso uart status register can inform which event has caused an interrupt (buffer full, buffer empty, parity error detected etc.) in accordance with peripheral interface. the register is reset when its status is read by the microcontroller. the iso uart configuration register enables the microcontroller to configure the iso uart and to choose between 5 or 3 v cards. bit uc4 (3 v/5 v) low means 5 v card, bit uc4 (3 v/5 v) high means 3 v card; conform peripheral interface. the selection of 3 or 5 v card has to be done before activation. after power-on, all iso uart registers are reset. the iso uart is configured in the reception mode. when the microcontroller wants to start a session, it sets the bits uc1 (start session) and uc0 (iso uart reset) in the uart configuration register and then sets bit start session low. when the first start bit on i/o is detected (sampling rate f clk /31), the uart sets the bit us2 (first start bit detected) in the status register which gives an interrupt on internal port int0 one clock pulse later. the convention is recognized on the first character of the atr and the uart configures itself in order to exchange direct data without parity processing with the microcontroller whatever the convention of the card is. bit uc1 (start session) must be reset by software. at the end of every character, the uart tests the parity and resets what is necessary for receiving another character. if no parity error is detected, the uart sets bit us1 (uart receive buffer full) in the status register which warns the microcontroller it has to read the character before the reception of the next one has been completed. the status register is reset when read from the controller. if a parity error has been detected, the uart pulls the i/o line low between 10.5 and 12 etu. it also sets the bits us1 (uart receive buffer full) and us3 (parity error detected during reception of a character) in the status register which warns the microcontroller that an error has occurred. the card is supposed to repeat the previous character.
1998 mar 20 15 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.6 iso uart reception flow chart. (1) fsd = first start detect. (2) the start session is reset by software. (3) the software may load the received character in the peripheral control at any time without any action on the iso uart. handbook, full pagewidth mgl335 convert and load character in reception buffer at 10 etu check parity (3) (2) parity error disable i/o buffer between 10 and 12 etu set bit buffer full at 10 etu reset reception part at 12 etu set bit reception parity error at 10 etu pull i/o line low from 10.5 to 11.75 etu 5th bit set convention if start session = 1 set fsd status register if fsd is enabled reset en fsd sample i/o at 186 and every 372 clk sample i/o every 31 clk inhibit i/o during 200 clk set enable fsd (1) 10th bit i/o = 0 y n clock starts stop; t/r = 1 start; and t/r = 0 start; t/r = 0 or lct = 1
1998 mar 20 16 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a when the controller needs to transmit data to the card, it first sets bit uc3 in the uart configuration register which configures the uart in the transmission mode. as soon as a character has been written in the uart transmit register, the uart makes the conversion, calculates the parity and starts the transmission on the rising edge of enable. when the character has been transmitted, it surveys the i/o line at 11 etu in order to know if an error has been detected by the card. if no error has occurred, the uart sets bit us0 (uart transmit buffer empty) in the status register and waits for the next character. if the next character has been written before 12 etu, the transmission will start at 12 etu. if it was written after 12 etu it will start on the rising edge of enable. if an error has occurred, it sets bits us0 and us4 (parity error detected during transmission of a character) which warns the microcontroller to rewrite the previous character in the uart transmit register. if the character has been rewritten before 13 etu, the transmission will start at 13 etu. if it has been written after 13 etu it will start on the rising edge of enable. when the transmission is completed, the microcontroller may set bit lct (last character to transmit) so that the uart will force the reception mode into ready to get the reply from the card at 12 etu. this bit must be reset before the end of the first reception. bit uc3 (transmit/receive) must be reset to enable the reception of the characters to follow. when the session is completed, the microcontroller re-initializes the whole uart by resetting bit uc0 (iso uart reset).
1998 mar 20 17 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.7 iso uart transmission flow chart. (1) the transmit register may be loaded just after reading from the status register. (2) the software must reset the last character but before completion of the first received character. handbook, full pagewidth mgl336 set transmit enable convert, calculate parity and load in transmit shift register sample i/o at 11 etu set bit transmission parity error and buffer empty at 11 etu reset transmit part and enable transmit at 13 etu shift every etu if transmit enable is set transmit register selected t/r = 0 10th bit shifted (1) (2) set i/o buffer in reception at 10 etu set bit buffer empty at 11 etu reset transmit part and enable transmit at 12 etu reset transmit part at 11 etu force reception mode y y n n stop parity error lct = 1 y n stop start; t/r
1998 mar 20 18 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a i/o buffer modes (see fig.8) the i/o buffer modes are: i/o buffer disabled i/o buffer in input, 20 k w pull-up resistor connected between i/o and v cc , i/o masked till 200 clock pulses i/o buffer in input, 20 k w pull-up resistor connected between i/o and v cc , i/o is sampled every 31 clock pulses i/o buffer in output, 20 k w pull-up resistor connected between i/o and v cc i/o buffer in output, i/o is pulled low by the n transistor of the buffer i/o buffer in output, i/o is pulled high or low by the p or n transistor. output ports extension in the lqfp64 version, 6 auxiliary output ports may be used for low frequency tasks (for example, keyboard scanning). these ports are push-pull output types (in accordance with use in software document). activation sequence when the card is inactive, v cc , clk, rst and i/o are low, with low impedance with respect to gnd. the step-up converter is stopped. the i/o is configured in the reception mode with a high impedance path to the iso uart, subsequently no spurious pulse from the card during power-up will be taken into account until i/o is enabled. when conditions are fulfilled (supply voltage present, card present, no hardware problems), the microcontroller may initiate an activation sequence by setting start low (t 0 ; see fig.9): 1. the step-up converter is started (t 1 ) 2. lis signal is disabled by internal signal enli, and v cc starts rising from 0 to 5 or 3 v (according to bit 4 of uart configuration register) with a controlled rise time of 0.1 v/ m s typically (t 2 ) 3. i/o buffer is enabled (t 3 ) 4. clock is sent to the card (t 4 ) 5. rst buffer is enabled (t 5 ). in order to allow a precise count of clock pulses during atr, a defined time window (t 3 ; t 5 ) is opened where the clock may be sent to the card by means of rstin (port p04). beyond this window, rstin has no more action on clock, and only monitors the cards rst contact (rst is the inverse of rstin). the sequencer is clocked by f int /64 which leads to a time interval t of 25 m s typical. thus t 1 =0to 1 64 t, t 2 =t 1 + 3 2 t, t 3 =t 1 + 4t, t 4 =t 3 to t 5 and t 5 =t 1 + 7t. deactivation sequence when the session is completed, the microcontroller sets start high. the circuit then executes an automatic deactivation sequence (see fig.10): 1. card reset (rst falls low) at t 10 2. clock is stopped at t 11 3. i/o becomes high impedance to the iso uart (t 12 ) 4. v cc falls to 0 v with typical 0.1 v/ m s slew rate (t 13 ) 5. the step-up converter is stopped and clk; rst, v cc and i/o become low impedance to gnd (t 14 ) 6. t 10 < 1 64 t; t 11 =t 10 + 1 2 t; t 12 =t 10 + t; t 13 =t 10 + 3 2 t; t 14 =t 10 + 5t. protections main hardware fault conditions are monitored by the circuit: overcurrent on v cc (in accordance with options as specified in table 3) short circuits between v cc and other contacts card take-off during transaction. when one of these problems is detected, the security logic block pulls the interrupt line (port p10) off low, in order to warn the microcontroller and initiates an automatic deactivation of the contacts. when the deactivation has been completed, the off line returns high, except if the problem was due to a card extraction in which case it remains low until a card is inserted.
1998 mar 20 19 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.8 i/o buffer modes. mbh638 12 34543416363343 1 handbook, full pagewidth i/o out in i/o buffer t r iso uart mode character reception without error character reception with error activation character reception without error forced deactivation character transmission without error character transmission with error fig.9 activation sequence. handbook, full pagewidth mgl337 t 3 t act pres off start f int /64 v step-up v cc i/o enrst rstin internal internal clk rst enli
1998 mar 20 20 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a fig.10 emergency deactivation sequence after a card take-off. handbook, full pagewidth mgl338 t de t 10 t 11 t 12 t 13 t 14 pres off start f int /64 clk rst v cc v step-up i/o enli internal
1998 mar 20 21 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a limiting values in accordance with the absolute maximum rating system (iec 134). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter conditions min. max. unit v dda analog supply voltage - 0.3 +6.5 v v ddd digital supply voltage - 0.3 +6.5 v v n all input voltages - 0.3 v dd + 0.5 v i n1 dc current into pins xtal1, xtal2, rxd, txd, reset, int1, t0 (port p34), p37, p00 to p03, p11 to p17, p20 to p23 and test1 to test4 - 5ma i n2 dc current from or to pins aux1 and aux2 - 10 +10 ma i n3 dc current from or to pins s1 to s5 - 30 +30 ma i n4 dc current into pin delay - 5 +10 ma i n5 dc current from or to pin pres - 5+5ma i n6 dc current from and to pins k0 to k5 - 5+5ma i n7 dc current from or into pin alarm (according to option choice) - 5+5ma p tot total power dissipation t amb = - 25 to +85 c - 500 mw t stg storage temperature - 55 +150 c v esd electrostatic discharge on pins i/o, v cc , rst, clk and pres - 6+6kv on other pins - 2+2kv t j junction temperature -- 125 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air lqfp64 70 k/w qfp44 60 k/w
1998 mar 20 22 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a characteristics v dd =5v; v ss =0v; t amb =25 c; for general purpose i/o ports refer to p80cl51 data sheet; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd supply voltage voltage superior, option dependant; note 1 2.5 - 6.0 v i dd(pd) supply current in power-down mode v dd = 5 or 3 v; card inactive - 100 -m a i dd(sm) supply current in sleep mode card powered but clock stopped; no load doubler option - 500 -m a tripler option - 700 -m a i dd(om) supply current operating mode unloaded; f xtal = 13 mhz; f clk = 6.5 mhz; f card = 3.25 mhz - 5.5 - ma v dd =3v; f xtal = 13 mhz; f clk = 3.25 mhz; f card = 3.25 mhz - 3 - ma v th(vdd) threshold voltage on v dd (falling) supervisor option 2 - 2.3 v 2.45 - 3v 3.8 - 4.5 v v hys(vthvdd) hysteresis on v th(vdd) 40 - 350 mv v th(delay) threshold voltage on pin delay - 1.38 - v v delay voltage on pin delay v dd - 0.5 - v dd v i delay output current at pin delay pin grounded (charge) - 1.5 - 1 - 0.4 m a v delay =v dd (discharge) 4 6.8 10 ma t w alarm pulse width c delay =10nf - 10 - ms alarm (open drain active high or low output) i oh high-level output current active low option; v oh =5v -- 10 m a v ol low-level output voltage active low option; i ol =2ma -- 0.4 v i ol low-level output current active high option; v ol =0v -- - 10 m a v oh high-level output voltage active high option; i oh = - 2ma v dd - 1 -- v crystal oscillator; note 2 f xtal crystal frequency 2 - 16 mhz f ext frequency of external signal applied on pin xtal1 0 - 16 mhz
1998 mar 20 23 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a step-up converter f int internal oscillation frequency 2 - 3 mhz v step-up voltage on pin s5 5 v card - 6.5 - v 3 v card - 4.5 - v low impedance supply (pin lis) v lis voltage on pin lis 0 - v dd v i lis current at pin lis -- 7 m a reset output to the card (pin rst) v o(rst) output voltage when inactive or when lis is used; i o(rst) =1ma - 0.3 - +0.4 v i o(rst) output current when inactive and pin grounded -- - 1ma v ol low-level output voltage i ol = 200 m a - 0.25 - +0.4 v v oh high-level output voltage i oh - 200 m a 5 v card 4 - v cc + 0.3 v 3 v card 2.4 - v cc + 0.3 v t r rise time c l =30pf -- 1 m s t f fall time c l =30pf -- 1 m s clock output to the card (pin clk) v o(clk) output voltage when inactive or when lis is used; i o(clk) =1ma - 0.3 - +0.4 v i o(clk) output current when inactive and pin grounded -- - 1ma v ol low-level output voltage i ol = 200 m a - 0.25 - +0.4 v v oh high-level output voltage i oh - 200 m av cc - 0.5 - v cc + 0.25 v t r rise time c l =30pf -- 15 ns t f fall time c l =30pf -- 15 ns f clk clock frequency 1 mhz idle con?guration 1 - 1.5 mhz low operating speed -- 2 mhz middle operating speed -- 4 mhz high operating speed -- 8 mhz d duty cycle c l =30pf 45 - 55 % symbol parameter conditions min. typ. max. unit
1998 mar 20 24 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a card supply voltage (pin v cc ) v o(vcc) card supply output voltage when inactive and when lis is used; i o(vcc) =1ma - 0.3 - +0.4 v when active; 5 v card no load 4.85 5.05 5.25 v static load 4.75 5.0 5.25 v dynamic loads on 200 nf capacitor 4.5 - 5.4 v when active; 3 v card no load 2.9 3.03 3.15 v static load 2.79 3 3.21 v dynamic loads on 200 nf capacitor 2.75 - 3.25 v i o(vcc) card supply output current when inactive and pin grounded -- - 1ma when active -- 20 ma limited -- note 1 ma sr slew rate on v cc (rise and fall) maximum load capacitor 250 nf (including typical 200 nf decoupling) 0.04 0.1 0.16 v/ m s data line (pin i/o) v o(i/o) output voltage when inactive or when lis is used; i o(i/o) =1ma - 0.3 - +0.4 v i o(i/o) output current when inactive and pin grounded -- - 1ma v ol low-level output voltage i/o con?gured as output; i ol =1ma - 0.25 - +0.3 v v oh high-level output voltage i/o con?gured as output; i oh 100 m a 0.8v cc - v cc + 0.25 v v il low-level input voltage i/o con?gured as input; i il =1ma 0 - 0.5 v v ih high-level input voltage i/o con?gured as input; i il = 100 m a 0.6v cc - v cc v t r rise time c l =30pf -- 1 m s t f fall time c l =30pf -- 1 m s protections i cc(sd) shutdown current at pin v cc - 00/30/60; note 1 - ma symbol parameter conditions min. typ. max. unit
1998 mar 20 25 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a notes 1. see table 3 for mask options. 2. the crystal oscillator is the same as option 3 of the p80cl51. timing t act activation sequence duration -- 225 m s t de deactivation sequence duration -- 150 m s t 3(start) start of the window for sending clock to the card -- 130 m s t 5(end) end of the window for sending clock to the card 140 --m s auxiliary outputs (aux1 and aux2) v ol low-level output voltage i ol =5ma -- 0.4 v v oh high-level output voltage i oh = - 5ma v dd - 1 -- v output ports from extension (k0 to k5) v ol low-level output voltage i ol =2ma -- 0.4 v v oh high-level output voltage i oh = - 2ma v dd - 1 -- v card presence input (pin pres) v il low-level input voltage i il = - 1ma -- 0.6 v v ih high-level input voltage i ih = 100 m a 0.7v dd -- v i ih high-level input current v ih = 5 v 0.2 - 3 m a symbol parameter conditions min. typ. max. unit
1998 mar 20 26 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... application information handbook, full pagewidth 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 4.7 nf keyboard 100 nf c1 c2 c3 c4 k1 k2 nc8 nc7 nc6 nc5 c5 c6 c7 c8 nc1 nc2 nc3 nc4 100 nf 47 nf 4.7 nf 100 nf TDA8005AG r7 + 5 v (logic) 1.5 w 1.5 w led2 led1 mmi-clk mmi-en tx rx reset mmi-req lis r8 card read unit c702 mgl339 from system controller + 5 v (logic) + 5 v (analog) 100 k w 5 v (analog) fig.11 possible gsm application.
1998 mar 20 27 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... ha ndbook, full pagewidth 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 7.15 mhz 33 pf 4.7 nf 33 pf display driver and display as e d7 d6 d5 d4 d3 d2 d1 d8 r/w v dd v dd keyboard 100 nf c8 c7 c6 c5 k1 k2 nc1 nc2 nc3 nc4 c4 c3 c2 c1 nc5 nc6 nc7 nc8 3 v 100 nf 47 nf 47 nf 47 nf 100 nf TDA8005AG r6 led1 led2 r7 card read unit lm01 mgl340 fig.12 possible stand-alone application.
1998 mar 20 28 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a mask options table 3 tda8005a option choice form function description option p00 p01 p02 p03 p04 rstin 3 s p05 start 3 s p06 strobe 3 s p07 enable 3 s p10 off 2 s p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 data 1 s p25 r/ w3s p26 reg1 3 s p27 reg0 3 s p30 p31 p32 int 1 s p33 p34 p35 aux1 3 s p36 aux2 3 s p37 table 4 description of used options; note 1 note 1. example: option 1 s indicates standard i/o, set to high state at power-on. option description 1 standard i/o 2 open-drain i/o 3 push-pull output s set to high state r set to low state
1998 mar 20 29 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a table 5 analog options features options step-up doubler tripler supervisor 2.3 v 3 v 4.5 v i/o low high impedance i/o pull-up 10 k w 20 k w 30 k w r-clk 0 100 w 150 w 200 w r-rst 0 80 w 130 w 180 w alarm active high active low pres active high active low ic protection no limitation 30 ma limitation 60 ma limitation
1998 mar 20 30 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a package outlines unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 95-12-19 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
1998 mar 20 31 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1998 mar 20 32 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp and qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for lqfp and qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all lqfp and qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for lqfp and qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 mar 20 33 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 mar 20 34 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a notes
1998 mar 20 35 philips semiconductors preliminary speci?cation low-power (3 v/5 v) smart card coupler tda8005a notes
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semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 435102/1200/01/pp36 date of release: 1998 mar 20 document order number: 9397 750 02512

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